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Commit 7cdb88a5 authored by Alexandre Julliard's avatar Alexandre Julliard
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include: Update the SYSTEM_PROCESS_INFORMATION structure.

Spotted by Alex Henrie. Signed-off-by: 's avatarAlexandre Julliard <julliard@winehq.org>
parent 1331a8ea
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Showing with 134 additions and 132 deletions
dlls/kernelbase/memory.c
View file @ 7cdb88a5
......@@ -109,7 +109,7 @@ void WINAPI DECLSPEC_HOTPATCH GetSystemInfo( SYSTEM_INFO *si )
&cpu_info, sizeof(cpu_info), NULL )))
return;
si->u.s.wProcessorArchitecture = cpu_info.Architecture;
si->u.s.wProcessorArchitecture = cpu_info.ProcessorArchitecture;
si->u.s.wReserved = 0;
si->dwPageSize = basic_info.PageSize;
si->lpMinimumApplicationAddress = basic_info.LowestUserAddress;
......@@ -117,13 +117,13 @@ void WINAPI DECLSPEC_HOTPATCH GetSystemInfo( SYSTEM_INFO *si )
si->dwActiveProcessorMask = basic_info.ActiveProcessorsAffinityMask;
si->dwNumberOfProcessors = basic_info.NumberOfProcessors;
si->dwAllocationGranularity = basic_info.AllocationGranularity;
si->wProcessorLevel = cpu_info.Level;
si->wProcessorRevision = cpu_info.Revision;
si->wProcessorLevel = cpu_info.ProcessorLevel;
si->wProcessorRevision = cpu_info.ProcessorRevision;
switch (cpu_info.Architecture)
switch (cpu_info.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_INTEL:
switch (cpu_info.Level)
switch (cpu_info.ProcessorLevel)
{
case 3: si->dwProcessorType = PROCESSOR_INTEL_386; break;
case 4: si->dwProcessorType = PROCESSOR_INTEL_486; break;
......@@ -133,7 +133,7 @@ void WINAPI DECLSPEC_HOTPATCH GetSystemInfo( SYSTEM_INFO *si )
}
break;
case PROCESSOR_ARCHITECTURE_PPC:
switch (cpu_info.Level)
switch (cpu_info.ProcessorLevel)
{
case 1: si->dwProcessorType = PROCESSOR_PPC_601; break;
case 3:
......@@ -148,7 +148,7 @@ void WINAPI DECLSPEC_HOTPATCH GetSystemInfo( SYSTEM_INFO *si )
si->dwProcessorType = PROCESSOR_AMD_X8664;
break;
case PROCESSOR_ARCHITECTURE_ARM:
switch (cpu_info.Level)
switch (cpu_info.ProcessorLevel)
{
case 4: si->dwProcessorType = PROCESSOR_ARM_7TDMI; break;
default: si->dwProcessorType = PROCESSOR_ARM920;
......@@ -158,7 +158,7 @@ void WINAPI DECLSPEC_HOTPATCH GetSystemInfo( SYSTEM_INFO *si )
si->dwProcessorType = 0;
break;
default:
FIXME( "Unknown processor architecture %x\n", cpu_info.Architecture );
FIXME( "Unknown processor architecture %x\n", cpu_info.ProcessorArchitecture );
si->dwProcessorType = 0;
break;
}
......
dlls/ntdll/tests/info.c
View file @ 7cdb88a5
......@@ -208,8 +208,9 @@ static void test_query_cpu(void)
ok( sizeof(sci) == ReturnLength, "Inconsistent length %d\n", ReturnLength);
/* Check if we have some return values */
if (winetest_debug > 1) trace("Processor FeatureSet : %08x\n", sci.FeatureSet);
ok( sci.FeatureSet != 0, "Expected some features for this processor, got %08x\n", sci.FeatureSet);
if (winetest_debug > 1) trace("Processor FeatureSet : %08x\n", sci.ProcessorFeatureBits);
ok( sci.ProcessorFeatureBits != 0, "Expected some features for this processor, got %08x\n",
sci.ProcessorFeatureBits);
}
static void test_query_performance(void)
......
dlls/ntdll/unix/signal_i386.c
View file @ 7cdb88a5
......@@ -847,7 +847,7 @@ static inline void save_context( struct xcontext *xcontext, const ucontext_t *si
context->ContextFlags |= CONTEXT_FLOATING_POINT | CONTEXT_EXTENDED_REGISTERS;
memcpy( context->ExtendedRegisters, fpux, sizeof(*fpux) );
if (!fpu) fpux_to_fpu( &context->FloatSave, fpux );
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xs = XState_sig(fpux)))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xs = XState_sig(fpux)))
{
context_init_xstate( context, xs );
xcontext->host_compaction_mask = xs->CompactionMask;
......@@ -975,11 +975,11 @@ void signal_restore_full_cpu_context(void)
{
struct syscall_xsave *xsave = get_syscall_xsave( get_syscall_frame() );
if (cpu_info.FeatureSet & CPU_FEATURE_XSAVE)
if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_XSAVE)
{
__asm__ volatile( "xrstor %0" : : "m"(*xsave), "a" (7), "d" (0) );
}
else if (cpu_info.FeatureSet & CPU_FEATURE_FXSR)
else if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_FXSR)
{
__asm__ volatile( "fxrstor %0" : : "m"(xsave->u.xsave) );
}
......@@ -1230,7 +1230,7 @@ NTSTATUS WINAPI NtSetContextThread( HANDLE handle, const CONTEXT *context )
else if (flags & CONTEXT_FLOATING_POINT)
{
struct syscall_xsave *xsave = get_syscall_xsave( frame );
if (cpu_info.FeatureSet & CPU_FEATURE_FXSR)
if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_FXSR)
{
fpu_to_fpux( &xsave->u.xsave, &context->FloatSave );
}
......@@ -1240,7 +1240,7 @@ NTSTATUS WINAPI NtSetContextThread( HANDLE handle, const CONTEXT *context )
}
xsave->xstate.mask |= XSTATE_MASK_LEGACY_FLOATING_POINT;
}
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xs = xstate_from_context( context )))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xs = xstate_from_context( context )))
{
struct syscall_xsave *xsave = get_syscall_xsave( frame );
CONTEXT_EX *context_ex = (CONTEXT_EX *)(context + 1);
......@@ -1326,7 +1326,7 @@ NTSTATUS WINAPI NtGetContextThread( HANDLE handle, CONTEXT *context )
}
if (needed_flags & CONTEXT_FLOATING_POINT)
{
if (!(cpu_info.FeatureSet & CPU_FEATURE_FXSR))
if (!(cpu_info.ProcessorFeatureBits & CPU_FEATURE_FXSR))
{
context->FloatSave = xsave->u.fsave;
}
......@@ -1385,7 +1385,7 @@ NTSTATUS WINAPI NtGetContextThread( HANDLE handle, CONTEXT *context )
x86_thread_data()->dr6 = context->Dr6;
x86_thread_data()->dr7 = context->Dr7;
}
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xstate = xstate_from_context( context )))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xstate = xstate_from_context( context )))
{
struct syscall_xsave *xsave = get_syscall_xsave( frame );
CONTEXT_EX *context_ex = (CONTEXT_EX *)(context + 1);
......@@ -2573,9 +2573,9 @@ void *signal_init_syscalls(void)
if (xstate_compaction_enabled)
syscall_dispatcher = __wine_syscall_dispatcher_xsavec;
else if (cpu_info.FeatureSet & CPU_FEATURE_XSAVE)
else if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_XSAVE)
syscall_dispatcher = __wine_syscall_dispatcher_xsave;
else if (cpu_info.FeatureSet & CPU_FEATURE_FXSR)
else if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_FXSR)
syscall_dispatcher = __wine_syscall_dispatcher_fxsave;
else
syscall_dispatcher = __wine_syscall_dispatcher;
......
dlls/ntdll/unix/signal_x86_64.c
View file @ 7cdb88a5
......@@ -1528,7 +1528,7 @@ static void save_context( struct xcontext *xcontext, const ucontext_t *sigcontex
context->ContextFlags |= CONTEXT_FLOATING_POINT;
context->u.FltSave = *FPU_sig(sigcontext);
context->MxCsr = context->u.FltSave.MxCsr;
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xs = XState_sig(FPU_sig(sigcontext))))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xs = XState_sig(FPU_sig(sigcontext))))
{
/* xcontext and sigcontext are both on the signal stack, so we can
* just reference sigcontext without overflowing 32 bit XState.Offset */
......@@ -1558,7 +1558,7 @@ static void restore_context( const struct xcontext *xcontext, ucontext_t *sigcon
amd64_thread_data()->dr7 = context->Dr7;
set_sigcontext( context, sigcontext );
if (FPU_sig(sigcontext)) *FPU_sig(sigcontext) = context->u.FltSave;
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xs = XState_sig(FPU_sig(sigcontext))))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xs = XState_sig(FPU_sig(sigcontext))))
xs->CompactionMask = xcontext->host_compaction_mask;
}
......@@ -1600,7 +1600,7 @@ void signal_restore_full_cpu_context(void)
{
struct syscall_xsave *xsave = get_syscall_xsave( get_syscall_frame() );
if (cpu_info.FeatureSet & CPU_FEATURE_XSAVE)
if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_XSAVE)
{
__asm__ volatile( "xrstor64 %0" : : "m"(xsave->xsave), "a" (7), "d" (0) );
}
......@@ -1907,7 +1907,7 @@ NTSTATUS WINAPI NtSetContextThread( HANDLE handle, const CONTEXT *context )
xsave->xsave = context->u.FltSave;
xsave->xstate.Mask |= XSTATE_MASK_LEGACY;
}
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xs = xstate_from_context( context )))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xs = xstate_from_context( context )))
{
CONTEXT_EX *context_ex = (CONTEXT_EX *)(context + 1);
......@@ -2044,7 +2044,7 @@ NTSTATUS WINAPI NtGetContextThread( HANDLE handle, CONTEXT *context )
amd64_thread_data()->dr6 = context->Dr6;
amd64_thread_data()->dr7 = context->Dr7;
}
if ((cpu_info.FeatureSet & CPU_FEATURE_AVX) && (xstate = xstate_from_context( context )))
if ((cpu_info.ProcessorFeatureBits & CPU_FEATURE_AVX) && (xstate = xstate_from_context( context )))
{
struct syscall_xsave *xsave = get_syscall_xsave( frame );
CONTEXT_EX *context_ex = (CONTEXT_EX *)(context + 1);
......@@ -2895,7 +2895,7 @@ void *signal_init_syscalls(void)
if (xstate_compaction_enabled)
syscall_dispatcher = __wine_syscall_dispatcher_xsavec;
else if (cpu_info.FeatureSet & CPU_FEATURE_XSAVE)
else if (cpu_info.ProcessorFeatureBits & CPU_FEATURE_XSAVE)
syscall_dispatcher = __wine_syscall_dispatcher_xsave;
else
syscall_dispatcher = __wine_syscall_dispatcher;
......
dlls/ntdll/unix/system.c
View file @ 7cdb88a5
......@@ -241,14 +241,14 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
unsigned int regs[4], regs2[4], regs3[4];
#if defined(__i386__)
info->Architecture = PROCESSOR_ARCHITECTURE_INTEL;
info->ProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL;
#elif defined(__x86_64__)
info->Architecture = PROCESSOR_ARCHITECTURE_AMD64;
info->ProcessorArchitecture = PROCESSOR_ARCHITECTURE_AMD64;
#endif
/* We're at least a 386 */
info->FeatureSet = CPU_FEATURE_VME | CPU_FEATURE_X86 | CPU_FEATURE_PGE;
info->Level = 3;
info->ProcessorFeatureBits = CPU_FEATURE_VME | CPU_FEATURE_X86 | CPU_FEATURE_PGE;
info->ProcessorLevel = 3;
if (!have_cpuid()) return;
......@@ -256,35 +256,35 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
if (regs[0]>=0x00000001) /* Check for supported cpuid version */
{
do_cpuid( 0x00000001, 0, regs2 ); /* get cpu features */
if (regs2[3] & (1 << 3 )) info->FeatureSet |= CPU_FEATURE_PSE;
if (regs2[3] & (1 << 4 )) info->FeatureSet |= CPU_FEATURE_TSC;
if (regs2[3] & (1 << 6 )) info->FeatureSet |= CPU_FEATURE_PAE;
if (regs2[3] & (1 << 8 )) info->FeatureSet |= CPU_FEATURE_CX8;
if (regs2[3] & (1 << 11)) info->FeatureSet |= CPU_FEATURE_SEP;
if (regs2[3] & (1 << 12)) info->FeatureSet |= CPU_FEATURE_MTRR;
if (regs2[3] & (1 << 15)) info->FeatureSet |= CPU_FEATURE_CMOV;
if (regs2[3] & (1 << 16)) info->FeatureSet |= CPU_FEATURE_PAT;
if (regs2[3] & (1 << 23)) info->FeatureSet |= CPU_FEATURE_MMX;
if (regs2[3] & (1 << 24)) info->FeatureSet |= CPU_FEATURE_FXSR;
if (regs2[3] & (1 << 25)) info->FeatureSet |= CPU_FEATURE_SSE;
if (regs2[3] & (1 << 26)) info->FeatureSet |= CPU_FEATURE_SSE2;
if (regs2[2] & (1 << 0 )) info->FeatureSet |= CPU_FEATURE_SSE3;
if (regs2[2] & (1 << 9 )) info->FeatureSet |= CPU_FEATURE_SSSE3;
if (regs2[2] & (1 << 13)) info->FeatureSet |= CPU_FEATURE_CX128;
if (regs2[2] & (1 << 19)) info->FeatureSet |= CPU_FEATURE_SSE41;
if (regs2[2] & (1 << 20)) info->FeatureSet |= CPU_FEATURE_SSE42;
if (regs2[2] & (1 << 27)) info->FeatureSet |= CPU_FEATURE_XSAVE;
if (regs2[2] & (1 << 28)) info->FeatureSet |= CPU_FEATURE_AVX;
if (regs2[3] & (1 << 3 )) info->ProcessorFeatureBits |= CPU_FEATURE_PSE;
if (regs2[3] & (1 << 4 )) info->ProcessorFeatureBits |= CPU_FEATURE_TSC;
if (regs2[3] & (1 << 6 )) info->ProcessorFeatureBits |= CPU_FEATURE_PAE;
if (regs2[3] & (1 << 8 )) info->ProcessorFeatureBits |= CPU_FEATURE_CX8;
if (regs2[3] & (1 << 11)) info->ProcessorFeatureBits |= CPU_FEATURE_SEP;
if (regs2[3] & (1 << 12)) info->ProcessorFeatureBits |= CPU_FEATURE_MTRR;
if (regs2[3] & (1 << 15)) info->ProcessorFeatureBits |= CPU_FEATURE_CMOV;
if (regs2[3] & (1 << 16)) info->ProcessorFeatureBits |= CPU_FEATURE_PAT;
if (regs2[3] & (1 << 23)) info->ProcessorFeatureBits |= CPU_FEATURE_MMX;
if (regs2[3] & (1 << 24)) info->ProcessorFeatureBits |= CPU_FEATURE_FXSR;
if (regs2[3] & (1 << 25)) info->ProcessorFeatureBits |= CPU_FEATURE_SSE;
if (regs2[3] & (1 << 26)) info->ProcessorFeatureBits |= CPU_FEATURE_SSE2;
if (regs2[2] & (1 << 0 )) info->ProcessorFeatureBits |= CPU_FEATURE_SSE3;
if (regs2[2] & (1 << 9 )) info->ProcessorFeatureBits |= CPU_FEATURE_SSSE3;
if (regs2[2] & (1 << 13)) info->ProcessorFeatureBits |= CPU_FEATURE_CX128;
if (regs2[2] & (1 << 19)) info->ProcessorFeatureBits |= CPU_FEATURE_SSE41;
if (regs2[2] & (1 << 20)) info->ProcessorFeatureBits |= CPU_FEATURE_SSE42;
if (regs2[2] & (1 << 27)) info->ProcessorFeatureBits |= CPU_FEATURE_XSAVE;
if (regs2[2] & (1 << 28)) info->ProcessorFeatureBits |= CPU_FEATURE_AVX;
if((regs2[3] & (1 << 26)) && (regs2[3] & (1 << 24)) && have_sse_daz_mode()) /* has SSE2 and FXSAVE/FXRSTOR */
info->FeatureSet |= CPU_FEATURE_DAZ;
info->ProcessorFeatureBits |= CPU_FEATURE_DAZ;
if (regs[0] >= 0x00000007)
{
do_cpuid( 0x00000007, 0, regs3 ); /* get extended features */
if (regs3[1] & (1 << 5)) info->FeatureSet |= CPU_FEATURE_AVX2;
if (regs3[1] & (1 << 5)) info->ProcessorFeatureBits |= CPU_FEATURE_AVX2;
}
if (info->FeatureSet & CPU_FEATURE_XSAVE)
if (info->ProcessorFeatureBits & CPU_FEATURE_XSAVE)
{
do_cpuid( 0x0000000d, 1, regs3 ); /* get XSAVE details */
if (regs3[0] & 2) xstate_compaction_enabled = TRUE;
......@@ -292,53 +292,53 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
if (regs[1] == AUTH && regs[3] == ENTI && regs[2] == CAMD)
{
info->Level = (regs2[0] >> 8) & 0xf; /* family */
if (info->Level == 0xf) /* AMD says to add the extended family to the family if family is 0xf */
info->Level += (regs2[0] >> 20) & 0xff;
info->ProcessorLevel = (regs2[0] >> 8) & 0xf; /* family */
if (info->ProcessorLevel == 0xf) /* AMD says to add the extended family to the family if family is 0xf */
info->ProcessorLevel += (regs2[0] >> 20) & 0xff;
/* repack model and stepping to make a "revision" */
info->Revision = ((regs2[0] >> 16) & 0xf) << 12; /* extended model */
info->Revision |= ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->Revision |= regs2[0] & 0xf; /* stepping */
info->ProcessorRevision = ((regs2[0] >> 16) & 0xf) << 12; /* extended model */
info->ProcessorRevision |= ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->ProcessorRevision |= regs2[0] & 0xf; /* stepping */
do_cpuid( 0x80000000, 0, regs ); /* get vendor cpuid level */
if (regs[0] >= 0x80000001)
{
do_cpuid( 0x80000001, 0, regs2 ); /* get vendor features */
if (regs2[2] & (1 << 2)) info->FeatureSet |= CPU_FEATURE_VIRT;
if (regs2[3] & (1 << 20)) info->FeatureSet |= CPU_FEATURE_NX;
if (regs2[3] & (1 << 27)) info->FeatureSet |= CPU_FEATURE_TSC;
if (regs2[3] & (1u << 31)) info->FeatureSet |= CPU_FEATURE_3DNOW;
if (regs2[2] & (1 << 2)) info->ProcessorFeatureBits |= CPU_FEATURE_VIRT;
if (regs2[3] & (1 << 20)) info->ProcessorFeatureBits |= CPU_FEATURE_NX;
if (regs2[3] & (1 << 27)) info->ProcessorFeatureBits |= CPU_FEATURE_TSC;
if (regs2[3] & (1u << 31)) info->ProcessorFeatureBits |= CPU_FEATURE_3DNOW;
}
}
else if (regs[1] == GENU && regs[3] == INEI && regs[2] == NTEL)
{
info->Level = ((regs2[0] >> 8) & 0xf) + ((regs2[0] >> 20) & 0xff); /* family + extended family */
if(info->Level == 15) info->Level = 6;
info->ProcessorLevel = ((regs2[0] >> 8) & 0xf) + ((regs2[0] >> 20) & 0xff); /* family + extended family */
if(info->ProcessorLevel == 15) info->ProcessorLevel = 6;
/* repack model and stepping to make a "revision" */
info->Revision = ((regs2[0] >> 16) & 0xf) << 12; /* extended model */
info->Revision |= ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->Revision |= regs2[0] & 0xf; /* stepping */
info->ProcessorRevision = ((regs2[0] >> 16) & 0xf) << 12; /* extended model */
info->ProcessorRevision |= ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->ProcessorRevision |= regs2[0] & 0xf; /* stepping */
if(regs2[2] & (1 << 5)) info->FeatureSet |= CPU_FEATURE_VIRT;
if(regs2[3] & (1 << 21)) info->FeatureSet |= CPU_FEATURE_DS;
if(regs2[2] & (1 << 5)) info->ProcessorFeatureBits |= CPU_FEATURE_VIRT;
if(regs2[3] & (1 << 21)) info->ProcessorFeatureBits |= CPU_FEATURE_DS;
do_cpuid( 0x80000000, 0, regs ); /* get vendor cpuid level */
if (regs[0] >= 0x80000001)
{
do_cpuid( 0x80000001, 0, regs2 ); /* get vendor features */
if (regs2[3] & (1 << 20)) info->FeatureSet |= CPU_FEATURE_NX;
if (regs2[3] & (1 << 27)) info->FeatureSet |= CPU_FEATURE_TSC;
if (regs2[3] & (1 << 20)) info->ProcessorFeatureBits |= CPU_FEATURE_NX;
if (regs2[3] & (1 << 27)) info->ProcessorFeatureBits |= CPU_FEATURE_TSC;
}
}
else
{
info->Level = (regs2[0] >> 8) & 0xf; /* family */
info->ProcessorLevel = (regs2[0] >> 8) & 0xf; /* family */
/* repack model and stepping to make a "revision" */
info->Revision = ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->Revision |= regs2[0] & 0xf; /* stepping */
info->ProcessorRevision = ((regs2[0] >> 4 ) & 0xf) << 8; /* model */
info->ProcessorRevision |= regs2[0] & 0xf; /* stepping */
}
}
}
......@@ -367,18 +367,18 @@ static inline void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
if ((s = strchr( value,'\n' ))) *s = 0;
if (!strcmp( line, "CPU architecture" ))
{
info->Level = atoi(value);
info->ProcessorLevel = atoi(value);
continue;
}
if (!strcmp( line, "CPU revision" ))
{
info->Revision = atoi(value);
info->ProcessorRevision = atoi(value);
continue;
}
if (!strcmp( line, "Features" ))
{
if (strstr(value, "crc32")) info->FeatureSet |= CPU_FEATURE_ARM_V8_CRC32;
if (strstr(value, "aes")) info->FeatureSet |= CPU_FEATURE_ARM_V8_CRYPTO;
if (strstr(value, "crc32")) info->ProcessorFeatureBits |= CPU_FEATURE_ARM_V8_CRC32;
if (strstr(value, "aes")) info->ProcessorFeatureBits |= CPU_FEATURE_ARM_V8_CRYPTO;
continue;
}
}
......@@ -391,15 +391,15 @@ static inline void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
valsize = sizeof(buf);
if (!sysctlbyname("hw.machine_arch", &buf, &valsize, NULL, 0) && sscanf(buf, "armv%i", &value) == 1)
info->Level = value;
info->ProcessorLevel = value;
valsize = sizeof(value);
if (!sysctlbyname("hw.floatingpoint", &value, &valsize, NULL, 0))
info->FeatureSet |= CPU_FEATURE_ARM_VFP_32;
info->ProcessorFeatureBits |= CPU_FEATURE_ARM_VFP_32;
#else
FIXME("CPU Feature detection not implemented.\n");
#endif
info->Architecture = PROCESSOR_ARCHITECTURE_ARM;
info->ProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
}
#elif defined(__aarch64__)
......@@ -426,18 +426,18 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
if ((s = strchr( value,'\n' ))) *s = 0;
if (!strcmp( line, "CPU architecture" ))
{
info->Level = atoi(value);
info->ProcessorLevel = atoi(value);
continue;
}
if (!strcmp( line, "CPU revision" ))
{
info->Revision = atoi(value);
info->ProcessorRevision = atoi(value);
continue;
}
if (!strcmp( line, "Features" ))
{
if (strstr(value, "crc32")) info->FeatureSet |= CPU_FEATURE_ARM_V8_CRC32;
if (strstr(value, "aes")) info->FeatureSet |= CPU_FEATURE_ARM_V8_CRYPTO;
if (strstr(value, "crc32")) info->ProcessorFeatureBits |= CPU_FEATURE_ARM_V8_CRC32;
if (strstr(value, "aes")) info->ProcessorFeatureBits |= CPU_FEATURE_ARM_V8_CRYPTO;
continue;
}
}
......@@ -446,8 +446,8 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
#else
FIXME("CPU Feature detection not implemented.\n");
#endif
info->Level = max(info->Level, 8);
info->Architecture = PROCESSOR_ARCHITECTURE_ARM64;
info->ProcessorLevel = max(info->ProcessorLevel, 8);
info->ProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM64;
}
#endif /* End architecture specific feature detection for CPUs */
......@@ -488,7 +488,8 @@ void init_cpu_info(void)
NtCurrentTeb()->Peb->NumberOfProcessors = num;
get_cpuinfo( &cpu_info );
TRACE( "<- CPU arch %d, level %d, rev %d, features 0x%x\n",
cpu_info.Architecture, cpu_info.Level, cpu_info.Revision, cpu_info.FeatureSet );
cpu_info.ProcessorArchitecture, cpu_info.ProcessorLevel, cpu_info.ProcessorRevision,
cpu_info.ProcessorFeatureBits );
}
static BOOL grow_logical_proc_buf( SYSTEM_LOGICAL_PROCESSOR_INFORMATION **pdata, DWORD *max_len )
......
include/winternl.h
View file @ 7cdb88a5
......@@ -2129,11 +2129,11 @@ typedef struct _SYSTEM_BASIC_INFORMATION {
/* System Information Class 0x01 */
typedef struct _SYSTEM_CPU_INFORMATION {
WORD Architecture;
WORD Level;
WORD Revision; /* combination of CPU model and stepping */
WORD Reserved; /* always zero */
DWORD FeatureSet; /* see bit flags below */
USHORT ProcessorArchitecture;
USHORT ProcessorLevel;
USHORT ProcessorRevision;
USHORT MaximumProcessors;
ULONG ProcessorFeatureBits;
} SYSTEM_CPU_INFORMATION, *PSYSTEM_CPU_INFORMATION;
/* definitions of bits in the Feature set for the x86 processors */
......
programs/wineboot/wineboot.c
View file @ 7cdb88a5
......@@ -286,7 +286,7 @@ static void create_user_shared_data(void)
data->NtBuildNumber = version.dwBuildNumber;
data->NtProductType = version.wProductType;
data->ProductTypeIsValid = TRUE;
data->NativeProcessorArchitecture = sci.Architecture;
data->NativeProcessorArchitecture = sci.ProcessorArchitecture;
data->NtMajorVersion = version.dwMajorVersion;
data->NtMinorVersion = version.dwMinorVersion;
data->SuiteMask = version.wSuiteMask;
......@@ -295,41 +295,41 @@ static void create_user_shared_data(void)
wcscpy( data->NtSystemRoot, L"C:\\windows" );
features = data->ProcessorFeatures;
switch (sci.Architecture)
switch (sci.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_INTEL:
case PROCESSOR_ARCHITECTURE_AMD64:
features[PF_COMPARE_EXCHANGE_DOUBLE] = !!(sci.FeatureSet & CPU_FEATURE_CX8);
features[PF_MMX_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_MMX);
features[PF_XMMI_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE);
features[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_3DNOW);
features[PF_RDTSC_INSTRUCTION_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_TSC);
features[PF_PAE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_PAE);
features[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE2);
features[PF_SSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE3);
features[PF_SSSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSSE3);
features[PF_XSAVE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_XSAVE);
features[PF_COMPARE_EXCHANGE128] = !!(sci.FeatureSet & CPU_FEATURE_CX128);
features[PF_SSE_DAZ_MODE_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_DAZ);
features[PF_NX_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_NX);
features[PF_SECOND_LEVEL_ADDRESS_TRANSLATION] = !!(sci.FeatureSet & CPU_FEATURE_2NDLEV);
features[PF_VIRT_FIRMWARE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_VIRT);
features[PF_RDWRFSGSBASE_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_RDFS);
features[PF_COMPARE_EXCHANGE_DOUBLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_CX8);
features[PF_MMX_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_MMX);
features[PF_XMMI_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSE);
features[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_3DNOW);
features[PF_RDTSC_INSTRUCTION_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_TSC);
features[PF_PAE_ENABLED] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_PAE);
features[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSE2);
features[PF_SSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSE3);
features[PF_SSSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSSE3);
features[PF_XSAVE_ENABLED] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_XSAVE);
features[PF_COMPARE_EXCHANGE128] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_CX128);
features[PF_SSE_DAZ_MODE_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_DAZ);
features[PF_NX_ENABLED] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_NX);
features[PF_SECOND_LEVEL_ADDRESS_TRANSLATION] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_2NDLEV);
features[PF_VIRT_FIRMWARE_ENABLED] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_VIRT);
features[PF_RDWRFSGSBASE_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_RDFS);
features[PF_FASTFAIL_AVAILABLE] = TRUE;
features[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE41);
features[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE42);
features[PF_AVX_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_AVX);
features[PF_AVX2_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_AVX2);
features[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSE41);
features[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_SSE42);
features[PF_AVX_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_AVX);
features[PF_AVX2_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_AVX2);
break;
case PROCESSOR_ARCHITECTURE_ARM:
features[PF_ARM_VFP_32_REGISTERS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_ARM_VFP_32);
features[PF_ARM_NEON_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_ARM_NEON);
features[PF_ARM_V8_INSTRUCTIONS_AVAILABLE] = (sci.Level >= 8);
features[PF_ARM_VFP_32_REGISTERS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_ARM_VFP_32);
features[PF_ARM_NEON_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_ARM_NEON);
features[PF_ARM_V8_INSTRUCTIONS_AVAILABLE] = (sci.ProcessorLevel >= 8);
break;
case PROCESSOR_ARCHITECTURE_ARM64:
features[PF_ARM_V8_INSTRUCTIONS_AVAILABLE] = TRUE;
features[PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_ARM_V8_CRC32);
features[PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_ARM_V8_CRYPTO);
features[PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_ARM_V8_CRC32);
features[PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE] = !!(sci.ProcessorFeatureBits & CPU_FEATURE_ARM_V8_CRYPTO);
break;
}
data->ActiveProcessorCount = NtCurrentTeb()->Peb->NumberOfProcessors;
......@@ -666,12 +666,12 @@ static void create_hardware_registry_keys(void)
if (NtPowerInformation( ProcessorInformation, NULL, 0, power_info, sizeof_power_info ))
memset( power_info, 0, sizeof_power_info );
switch (sci.Architecture)
switch (sci.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_ARM:
case PROCESSOR_ARCHITECTURE_ARM64:
swprintf( id, ARRAY_SIZE(id), L"ARM Family %u Model %u Revision %u",
sci.Level, HIBYTE(sci.Revision), LOBYTE(sci.Revision) );
sci.ProcessorLevel, HIBYTE(sci.ProcessorRevision), LOBYTE(sci.ProcessorRevision) );
break;
case PROCESSOR_ARCHITECTURE_AMD64:
......@@ -691,7 +691,7 @@ static void create_hardware_registry_keys(void)
return;
}
switch (sci.Architecture)
switch (sci.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_ARM:
case PROCESSOR_ARCHITECTURE_ARM64:
......@@ -705,8 +705,8 @@ static void create_hardware_registry_keys(void)
break;
}
if (sci.Architecture == PROCESSOR_ARCHITECTURE_ARM ||
sci.Architecture == PROCESSOR_ARCHITECTURE_ARM64 ||
if (sci.ProcessorArchitecture == PROCESSOR_ARCHITECTURE_ARM ||
sci.ProcessorArchitecture == PROCESSOR_ARCHITECTURE_ARM64 ||
RegCreateKeyExW( system_key, L"FloatingPointProcessor", 0, NULL, REG_OPTION_VOLATILE,
KEY_ALL_ACCESS, NULL, &fpu_key, NULL ))
fpu_key = 0;
......@@ -722,7 +722,7 @@ static void create_hardware_registry_keys(void)
if (!RegCreateKeyExW( cpu_key, numW, 0, NULL, REG_OPTION_VOLATILE,
KEY_ALL_ACCESS, NULL, &hkey, NULL ))
{
RegSetValueExW( hkey, L"FeatureSet", 0, REG_DWORD, (BYTE *)&sci.FeatureSet, sizeof(DWORD) );
RegSetValueExW( hkey, L"FeatureSet", 0, REG_DWORD, (BYTE *)&sci.ProcessorFeatureBits, sizeof(DWORD) );
set_reg_value( hkey, L"Identifier", id );
/* TODO: report ARM properly */
set_reg_value( hkey, L"ProcessorNameString", namestr );
......@@ -730,8 +730,8 @@ static void create_hardware_registry_keys(void)
RegSetValueExW( hkey, L"~MHz", 0, REG_DWORD, (BYTE *)&power_info[i].MaxMhz, sizeof(DWORD) );
RegCloseKey( hkey );
}
if (sci.Architecture != PROCESSOR_ARCHITECTURE_ARM &&
sci.Architecture != PROCESSOR_ARCHITECTURE_ARM64 &&
if (sci.ProcessorArchitecture != PROCESSOR_ARCHITECTURE_ARM &&
sci.ProcessorArchitecture != PROCESSOR_ARCHITECTURE_ARM64 &&
!RegCreateKeyExW( fpu_key, numW, 0, NULL, REG_OPTION_VOLATILE,
KEY_ALL_ACCESS, NULL, &hkey, NULL ))
{
......@@ -776,7 +776,7 @@ static void create_environment_registry_keys( void )
swprintf( buffer, ARRAY_SIZE(buffer), L"%u", NtCurrentTeb()->Peb->NumberOfProcessors );
set_reg_value( env_key, L"NUMBER_OF_PROCESSORS", buffer );
switch (sci.Architecture)
switch (sci.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_AMD64:
arch = L"AMD64";
......@@ -790,12 +790,12 @@ static void create_environment_registry_keys( void )
}
set_reg_value( env_key, L"PROCESSOR_ARCHITECTURE", arch );
switch (sci.Architecture)
switch (sci.ProcessorArchitecture)
{
case PROCESSOR_ARCHITECTURE_ARM:
case PROCESSOR_ARCHITECTURE_ARM64:
swprintf( buffer, ARRAY_SIZE(buffer), L"ARM Family %u Model %u Revision %u",
sci.Level, HIBYTE(sci.Revision), LOBYTE(sci.Revision) );
sci.ProcessorLevel, HIBYTE(sci.ProcessorRevision), LOBYTE(sci.ProcessorRevision) );
break;
case PROCESSOR_ARCHITECTURE_AMD64:
......@@ -808,10 +808,10 @@ static void create_environment_registry_keys( void )
}
set_reg_value( env_key, L"PROCESSOR_IDENTIFIER", buffer );
swprintf( buffer, ARRAY_SIZE(buffer), L"%u", sci.Level );
swprintf( buffer, ARRAY_SIZE(buffer), L"%u", sci.ProcessorLevel );
set_reg_value( env_key, L"PROCESSOR_LEVEL", buffer );
swprintf( buffer, ARRAY_SIZE(buffer), L"%04x", sci.Revision );
swprintf( buffer, ARRAY_SIZE(buffer), L"%04x", sci.ProcessorRevision );
set_reg_value( env_key, L"PROCESSOR_REVISION", buffer );
RegCloseKey( env_key );
......
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