Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
W
wine-cw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Registry
Registry
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
wine
wine-cw
Commits
771463ad
Commit
771463ad
authored
Apr 03, 2020
by
Rémi Bernon
Committed by
Alexandre Julliard
Apr 03, 2020
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
winedbg: Add gdb register types to the register maps.
Signed-off-by:
Rémi Bernon
<
rbernon@codeweavers.com
>
Signed-off-by:
Alexandre Julliard
<
julliard@winehq.org
>
parent
a650b3d8
Hide whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
195 additions
and
194 deletions
+195
-194
be_arm.c
programs/winedbg/be_arm.c
+18
-18
be_arm64.c
programs/winedbg/be_arm64.c
+35
-35
be_cpu.h
programs/winedbg/be_cpu.h
+1
-0
be_i386.c
programs/winedbg/be_i386.c
+43
-43
be_ppc.c
programs/winedbg/be_ppc.c
+39
-39
be_x86_64.c
programs/winedbg/be_x86_64.c
+59
-59
No files found.
programs/winedbg/be_arm.c
View file @
771463ad
...
@@ -1900,26 +1900,26 @@ static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx)
...
@@ -1900,26 +1900,26 @@ static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
}
#define REG(f,n,
r,gs) {f, n
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
#define REG(f,n,
t,r,gs) {f, n, t
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static
struct
gdb_register
be_arm_gdb_register_map
[]
=
{
static
struct
gdb_register
be_arm_gdb_register_map
[]
=
{
REG
(
"core"
,
"r0"
,
R0
,
4
),
REG
(
"core"
,
"r0"
,
NULL
,
R0
,
4
),
REG
(
NULL
,
"r1"
,
R1
,
4
),
REG
(
NULL
,
"r1"
,
NULL
,
R1
,
4
),
REG
(
NULL
,
"r2"
,
R2
,
4
),
REG
(
NULL
,
"r2"
,
NULL
,
R2
,
4
),
REG
(
NULL
,
"r3"
,
R3
,
4
),
REG
(
NULL
,
"r3"
,
NULL
,
R3
,
4
),
REG
(
NULL
,
"r4"
,
R4
,
4
),
REG
(
NULL
,
"r4"
,
NULL
,
R4
,
4
),
REG
(
NULL
,
"r5"
,
R5
,
4
),
REG
(
NULL
,
"r5"
,
NULL
,
R5
,
4
),
REG
(
NULL
,
"r6"
,
R6
,
4
),
REG
(
NULL
,
"r6"
,
NULL
,
R6
,
4
),
REG
(
NULL
,
"r7"
,
R7
,
4
),
REG
(
NULL
,
"r7"
,
NULL
,
R7
,
4
),
REG
(
NULL
,
"r8"
,
R8
,
4
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
,
4
),
REG
(
NULL
,
"r9"
,
R9
,
4
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
,
4
),
REG
(
NULL
,
"r10"
,
R10
,
4
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
,
4
),
REG
(
NULL
,
"r11"
,
R11
,
4
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
,
4
),
REG
(
NULL
,
"r12"
,
R12
,
4
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
,
4
),
REG
(
NULL
,
"sp"
,
Sp
,
4
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
,
4
),
REG
(
NULL
,
"lr"
,
Lr
,
4
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
,
4
),
REG
(
NULL
,
"pc"
,
Pc
,
4
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
,
4
),
REG
(
NULL
,
"cpsr"
,
Cpsr
,
4
),
REG
(
NULL
,
"cpsr"
,
NULL
,
Cpsr
,
4
),
};
};
struct
backend_cpu
be_arm
=
struct
backend_cpu
be_arm
=
...
...
programs/winedbg/be_arm64.c
View file @
771463ad
...
@@ -289,43 +289,43 @@ static BOOL be_arm64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
...
@@ -289,43 +289,43 @@ static BOOL be_arm64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
}
#define REG(f,n,
r,gs) {f, n
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
#define REG(f,n,
t,r,gs) {f, n, t
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static
struct
gdb_register
be_arm64_gdb_register_map
[]
=
{
static
struct
gdb_register
be_arm64_gdb_register_map
[]
=
{
REG
(
"core"
,
"x0"
,
u
.
s
.
X0
,
8
),
REG
(
"core"
,
"x0"
,
NULL
,
u
.
s
.
X0
,
8
),
REG
(
NULL
,
"x1"
,
u
.
s
.
X1
,
8
),
REG
(
NULL
,
"x1"
,
NULL
,
u
.
s
.
X1
,
8
),
REG
(
NULL
,
"x2"
,
u
.
s
.
X2
,
8
),
REG
(
NULL
,
"x2"
,
NULL
,
u
.
s
.
X2
,
8
),
REG
(
NULL
,
"x3"
,
u
.
s
.
X3
,
8
),
REG
(
NULL
,
"x3"
,
NULL
,
u
.
s
.
X3
,
8
),
REG
(
NULL
,
"x4"
,
u
.
s
.
X4
,
8
),
REG
(
NULL
,
"x4"
,
NULL
,
u
.
s
.
X4
,
8
),
REG
(
NULL
,
"x5"
,
u
.
s
.
X5
,
8
),
REG
(
NULL
,
"x5"
,
NULL
,
u
.
s
.
X5
,
8
),
REG
(
NULL
,
"x6"
,
u
.
s
.
X6
,
8
),
REG
(
NULL
,
"x6"
,
NULL
,
u
.
s
.
X6
,
8
),
REG
(
NULL
,
"x7"
,
u
.
s
.
X7
,
8
),
REG
(
NULL
,
"x7"
,
NULL
,
u
.
s
.
X7
,
8
),
REG
(
NULL
,
"x8"
,
u
.
s
.
X8
,
8
),
REG
(
NULL
,
"x8"
,
NULL
,
u
.
s
.
X8
,
8
),
REG
(
NULL
,
"x9"
,
u
.
s
.
X9
,
8
),
REG
(
NULL
,
"x9"
,
NULL
,
u
.
s
.
X9
,
8
),
REG
(
NULL
,
"x10"
,
u
.
s
.
X10
,
8
),
REG
(
NULL
,
"x10"
,
NULL
,
u
.
s
.
X10
,
8
),
REG
(
NULL
,
"x11"
,
u
.
s
.
X11
,
8
),
REG
(
NULL
,
"x11"
,
NULL
,
u
.
s
.
X11
,
8
),
REG
(
NULL
,
"x12"
,
u
.
s
.
X12
,
8
),
REG
(
NULL
,
"x12"
,
NULL
,
u
.
s
.
X12
,
8
),
REG
(
NULL
,
"x13"
,
u
.
s
.
X13
,
8
),
REG
(
NULL
,
"x13"
,
NULL
,
u
.
s
.
X13
,
8
),
REG
(
NULL
,
"x14"
,
u
.
s
.
X14
,
8
),
REG
(
NULL
,
"x14"
,
NULL
,
u
.
s
.
X14
,
8
),
REG
(
NULL
,
"x15"
,
u
.
s
.
X15
,
8
),
REG
(
NULL
,
"x15"
,
NULL
,
u
.
s
.
X15
,
8
),
REG
(
NULL
,
"x16"
,
u
.
s
.
X16
,
8
),
REG
(
NULL
,
"x16"
,
NULL
,
u
.
s
.
X16
,
8
),
REG
(
NULL
,
"x17"
,
u
.
s
.
X17
,
8
),
REG
(
NULL
,
"x17"
,
NULL
,
u
.
s
.
X17
,
8
),
REG
(
NULL
,
"x18"
,
u
.
s
.
X18
,
8
),
REG
(
NULL
,
"x18"
,
NULL
,
u
.
s
.
X18
,
8
),
REG
(
NULL
,
"x19"
,
u
.
s
.
X19
,
8
),
REG
(
NULL
,
"x19"
,
NULL
,
u
.
s
.
X19
,
8
),
REG
(
NULL
,
"x20"
,
u
.
s
.
X20
,
8
),
REG
(
NULL
,
"x20"
,
NULL
,
u
.
s
.
X20
,
8
),
REG
(
NULL
,
"x21"
,
u
.
s
.
X21
,
8
),
REG
(
NULL
,
"x21"
,
NULL
,
u
.
s
.
X21
,
8
),
REG
(
NULL
,
"x22"
,
u
.
s
.
X22
,
8
),
REG
(
NULL
,
"x22"
,
NULL
,
u
.
s
.
X22
,
8
),
REG
(
NULL
,
"x23"
,
u
.
s
.
X23
,
8
),
REG
(
NULL
,
"x23"
,
NULL
,
u
.
s
.
X23
,
8
),
REG
(
NULL
,
"x24"
,
u
.
s
.
X24
,
8
),
REG
(
NULL
,
"x24"
,
NULL
,
u
.
s
.
X24
,
8
),
REG
(
NULL
,
"x25"
,
u
.
s
.
X25
,
8
),
REG
(
NULL
,
"x25"
,
NULL
,
u
.
s
.
X25
,
8
),
REG
(
NULL
,
"x26"
,
u
.
s
.
X26
,
8
),
REG
(
NULL
,
"x26"
,
NULL
,
u
.
s
.
X26
,
8
),
REG
(
NULL
,
"x27"
,
u
.
s
.
X27
,
8
),
REG
(
NULL
,
"x27"
,
NULL
,
u
.
s
.
X27
,
8
),
REG
(
NULL
,
"x28"
,
u
.
s
.
X28
,
8
),
REG
(
NULL
,
"x28"
,
NULL
,
u
.
s
.
X28
,
8
),
REG
(
NULL
,
"x29"
,
u
.
s
.
Fp
,
8
),
REG
(
NULL
,
"x29"
,
NULL
,
u
.
s
.
Fp
,
8
),
REG
(
NULL
,
"x30"
,
u
.
s
.
Lr
,
8
),
REG
(
NULL
,
"x30"
,
NULL
,
u
.
s
.
Lr
,
8
),
REG
(
NULL
,
"sp"
,
Sp
,
8
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
,
8
),
REG
(
NULL
,
"pc"
,
Pc
,
8
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
,
8
),
REG
(
NULL
,
"cpsr"
,
Cpsr
,
4
),
REG
(
NULL
,
"cpsr"
,
"cpsr_flags"
,
Cpsr
,
4
),
};
};
struct
backend_cpu
be_arm64
=
struct
backend_cpu
be_arm64
=
...
...
programs/winedbg/be_cpu.h
View file @
771463ad
...
@@ -26,6 +26,7 @@ struct gdb_register
...
@@ -26,6 +26,7 @@ struct gdb_register
{
{
const
char
*
feature
;
const
char
*
feature
;
const
char
*
name
;
const
char
*
name
;
const
char
*
type
;
size_t
ctx_offset
;
size_t
ctx_offset
;
size_t
ctx_length
;
size_t
ctx_length
;
size_t
gdb_length
;
size_t
gdb_length
;
...
...
programs/winedbg/be_i386.c
View file @
771463ad
...
@@ -865,51 +865,51 @@ static BOOL be_i386_set_context(HANDLE thread, const dbg_ctx_t *ctx)
...
@@ -865,51 +865,51 @@ static BOOL be_i386_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
Wow64SetThreadContext
(
thread
,
&
ctx
->
x86
);
return
Wow64SetThreadContext
(
thread
,
&
ctx
->
x86
);
}
}
#define REG(f,n,
r,gs) {f, n
, FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r), gs}
#define REG(f,n,
t,r,gs) {f, n, t
, FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r), gs}
static
struct
gdb_register
be_i386_gdb_register_map
[]
=
{
static
struct
gdb_register
be_i386_gdb_register_map
[]
=
{
REG
(
"core"
,
"eax"
,
Eax
,
4
),
REG
(
"core"
,
"eax"
,
NULL
,
Eax
,
4
),
REG
(
NULL
,
"ecx"
,
Ecx
,
4
),
REG
(
NULL
,
"ecx"
,
NULL
,
Ecx
,
4
),
REG
(
NULL
,
"edx"
,
Edx
,
4
),
REG
(
NULL
,
"edx"
,
NULL
,
Edx
,
4
),
REG
(
NULL
,
"ebx"
,
Ebx
,
4
),
REG
(
NULL
,
"ebx"
,
NULL
,
Ebx
,
4
),
REG
(
NULL
,
"esp"
,
Esp
,
4
),
REG
(
NULL
,
"esp"
,
"data_ptr"
,
Esp
,
4
),
REG
(
NULL
,
"ebp"
,
Ebp
,
4
),
REG
(
NULL
,
"ebp"
,
"data_ptr"
,
Ebp
,
4
),
REG
(
NULL
,
"esi"
,
Esi
,
4
),
REG
(
NULL
,
"esi"
,
NULL
,
Esi
,
4
),
REG
(
NULL
,
"edi"
,
Edi
,
4
),
REG
(
NULL
,
"edi"
,
NULL
,
Edi
,
4
),
REG
(
NULL
,
"eip"
,
Eip
,
4
),
REG
(
NULL
,
"eip"
,
"code_ptr"
,
Eip
,
4
),
REG
(
NULL
,
"eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"cs"
,
SegCs
,
4
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
,
4
),
REG
(
NULL
,
"ss"
,
SegSs
,
4
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
,
4
),
REG
(
NULL
,
"ds"
,
SegDs
,
4
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
,
4
),
REG
(
NULL
,
"es"
,
SegEs
,
4
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
,
4
),
REG
(
NULL
,
"fs"
,
SegFs
,
4
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
,
4
),
REG
(
NULL
,
"gs"
,
SegGs
,
4
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
,
4
),
{
NULL
,
"st0"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
0
]),
10
,
10
},
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
0
]),
10
,
10
},
{
NULL
,
"st1"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
10
]),
10
,
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
10
]),
10
,
10
},
{
NULL
,
"st2"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
20
]),
10
,
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
20
]),
10
,
10
},
{
NULL
,
"st3"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
30
]),
10
,
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
30
]),
10
,
10
},
{
NULL
,
"st4"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
40
]),
10
,
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
40
]),
10
,
10
},
{
NULL
,
"st5"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
50
]),
10
,
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
50
]),
10
,
10
},
{
NULL
,
"st6"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
60
]),
10
,
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
60
]),
10
,
10
},
{
NULL
,
"st7"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
70
]),
10
,
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
70
]),
10
,
10
},
{
NULL
,
"fctrl"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ControlWord
),
2
,
4
},
{
NULL
,
"fctrl"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ControlWord
),
2
,
4
},
{
NULL
,
"fstat"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
StatusWord
),
2
,
4
},
{
NULL
,
"fstat"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
StatusWord
),
2
,
4
},
{
NULL
,
"ftag"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
TagWord
),
2
,
4
},
{
NULL
,
"ftag"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
TagWord
),
2
,
4
},
{
NULL
,
"fiseg"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
),
2
,
4
},
{
NULL
,
"fiseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
),
2
,
4
},
REG
(
NULL
,
"fioff"
,
FloatSave
.
ErrorOffset
,
4
),
REG
(
NULL
,
"fioff"
,
NULL
,
FloatSave
.
ErrorOffset
,
4
),
{
NULL
,
"foseg"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
DataSelector
),
2
,
4
},
{
NULL
,
"foseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
DataSelector
),
2
,
4
},
REG
(
NULL
,
"fooff"
,
FloatSave
.
DataOffset
,
4
),
REG
(
NULL
,
"fooff"
,
NULL
,
FloatSave
.
DataOffset
,
4
),
{
NULL
,
"fop"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
)
+
2
,
2
,
4
},
{
NULL
,
"fop"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
)
+
2
,
2
,
4
},
{
"sse"
,
"xmm0"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
0
]),
16
,
16
},
{
"sse"
,
"xmm0"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
0
]),
16
,
16
},
{
NULL
,
"xmm1"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
1
]),
16
,
16
},
{
NULL
,
"xmm1"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
1
]),
16
,
16
},
{
NULL
,
"xmm2"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
2
]),
16
,
16
},
{
NULL
,
"xmm2"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
2
]),
16
,
16
},
{
NULL
,
"xmm3"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
3
]),
16
,
16
},
{
NULL
,
"xmm3"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
3
]),
16
,
16
},
{
NULL
,
"xmm4"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
4
]),
16
,
16
},
{
NULL
,
"xmm4"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
4
]),
16
,
16
},
{
NULL
,
"xmm5"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
5
]),
16
,
16
},
{
NULL
,
"xmm5"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
5
]),
16
,
16
},
{
NULL
,
"xmm6"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
6
]),
16
,
16
},
{
NULL
,
"xmm6"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
6
]),
16
,
16
},
{
NULL
,
"xmm7"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
7
]),
16
,
16
},
{
NULL
,
"xmm7"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
7
]),
16
,
16
},
{
NULL
,
"mxcsr"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
MxCsr
),
4
,
4
},
{
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
MxCsr
),
4
,
4
},
};
};
struct
backend_cpu
be_i386
=
struct
backend_cpu
be_i386
=
...
...
programs/winedbg/be_ppc.c
View file @
771463ad
...
@@ -191,47 +191,47 @@ static BOOL be_ppc_set_context(HANDLE thread, const dbg_ctx_t *ctx)
...
@@ -191,47 +191,47 @@ static BOOL be_ppc_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
}
#define REG(f,n,
r,gs) {f, n
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
#define REG(f,n,
t,r,gs) {f, n, t
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static
struct
gdb_register
be_ppc_gdb_register_map
[]
=
{
static
struct
gdb_register
be_ppc_gdb_register_map
[]
=
{
REG
(
"core"
,
"r0"
,
Gpr0
,
4
),
REG
(
"core"
,
"r0"
,
NULL
,
Gpr0
,
4
),
REG
(
NULL
,
"r1"
,
Gpr1
,
4
),
REG
(
NULL
,
"r1"
,
NULL
,
Gpr1
,
4
),
REG
(
NULL
,
"r2"
,
Gpr2
,
4
),
REG
(
NULL
,
"r2"
,
NULL
,
Gpr2
,
4
),
REG
(
NULL
,
"r3"
,
Gpr3
,
4
),
REG
(
NULL
,
"r3"
,
NULL
,
Gpr3
,
4
),
REG
(
NULL
,
"r4"
,
Gpr4
,
4
),
REG
(
NULL
,
"r4"
,
NULL
,
Gpr4
,
4
),
REG
(
NULL
,
"r5"
,
Gpr5
,
4
),
REG
(
NULL
,
"r5"
,
NULL
,
Gpr5
,
4
),
REG
(
NULL
,
"r6"
,
Gpr6
,
4
),
REG
(
NULL
,
"r6"
,
NULL
,
Gpr6
,
4
),
REG
(
NULL
,
"r7"
,
Gpr7
,
4
),
REG
(
NULL
,
"r7"
,
NULL
,
Gpr7
,
4
),
REG
(
NULL
,
"r8"
,
Gpr8
,
4
),
REG
(
NULL
,
"r8"
,
NULL
,
Gpr8
,
4
),
REG
(
NULL
,
"r9"
,
Gpr9
,
4
),
REG
(
NULL
,
"r9"
,
NULL
,
Gpr9
,
4
),
REG
(
NULL
,
"r10"
,
Gpr10
,
4
),
REG
(
NULL
,
"r10"
,
NULL
,
Gpr10
,
4
),
REG
(
NULL
,
"r11"
,
Gpr11
,
4
),
REG
(
NULL
,
"r11"
,
NULL
,
Gpr11
,
4
),
REG
(
NULL
,
"r12"
,
Gpr12
,
4
),
REG
(
NULL
,
"r12"
,
NULL
,
Gpr12
,
4
),
REG
(
NULL
,
"r13"
,
Gpr13
,
4
),
REG
(
NULL
,
"r13"
,
NULL
,
Gpr13
,
4
),
REG
(
NULL
,
"r14"
,
Gpr14
,
4
),
REG
(
NULL
,
"r14"
,
NULL
,
Gpr14
,
4
),
REG
(
NULL
,
"r15"
,
Gpr15
,
4
),
REG
(
NULL
,
"r15"
,
NULL
,
Gpr15
,
4
),
REG
(
NULL
,
"r16"
,
Gpr16
,
4
),
REG
(
NULL
,
"r16"
,
NULL
,
Gpr16
,
4
),
REG
(
NULL
,
"r17"
,
Gpr17
,
4
),
REG
(
NULL
,
"r17"
,
NULL
,
Gpr17
,
4
),
REG
(
NULL
,
"r18"
,
Gpr18
,
4
),
REG
(
NULL
,
"r18"
,
NULL
,
Gpr18
,
4
),
REG
(
NULL
,
"r19"
,
Gpr19
,
4
),
REG
(
NULL
,
"r19"
,
NULL
,
Gpr19
,
4
),
REG
(
NULL
,
"r20"
,
Gpr20
,
4
),
REG
(
NULL
,
"r20"
,
NULL
,
Gpr20
,
4
),
REG
(
NULL
,
"r21"
,
Gpr21
,
4
),
REG
(
NULL
,
"r21"
,
NULL
,
Gpr21
,
4
),
REG
(
NULL
,
"r22"
,
Gpr22
,
4
),
REG
(
NULL
,
"r22"
,
NULL
,
Gpr22
,
4
),
REG
(
NULL
,
"r23"
,
Gpr23
,
4
),
REG
(
NULL
,
"r23"
,
NULL
,
Gpr23
,
4
),
REG
(
NULL
,
"r24"
,
Gpr24
,
4
),
REG
(
NULL
,
"r24"
,
NULL
,
Gpr24
,
4
),
REG
(
NULL
,
"r25"
,
Gpr25
,
4
),
REG
(
NULL
,
"r25"
,
NULL
,
Gpr25
,
4
),
REG
(
NULL
,
"r26"
,
Gpr26
,
4
),
REG
(
NULL
,
"r26"
,
NULL
,
Gpr26
,
4
),
REG
(
NULL
,
"r27"
,
Gpr27
,
4
),
REG
(
NULL
,
"r27"
,
NULL
,
Gpr27
,
4
),
REG
(
NULL
,
"r28"
,
Gpr28
,
4
),
REG
(
NULL
,
"r28"
,
NULL
,
Gpr28
,
4
),
REG
(
NULL
,
"r29"
,
Gpr29
,
4
),
REG
(
NULL
,
"r29"
,
NULL
,
Gpr29
,
4
),
REG
(
NULL
,
"r30"
,
Gpr30
,
4
),
REG
(
NULL
,
"r30"
,
NULL
,
Gpr30
,
4
),
REG
(
NULL
,
"r31"
,
Gpr31
,
4
),
REG
(
NULL
,
"r31"
,
NULL
,
Gpr31
,
4
),
REG
(
NULL
,
"pc"
,
Iar
,
4
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Iar
,
4
),
REG
(
NULL
,
"msr"
,
Msr
,
4
),
REG
(
NULL
,
"msr"
,
NULL
,
Msr
,
4
),
REG
(
NULL
,
"cr"
,
Cr
,
4
),
REG
(
NULL
,
"cr"
,
NULL
,
Cr
,
4
),
REG
(
NULL
,
"lr"
,
Lr
,
4
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
,
4
),
REG
(
NULL
,
"ctr"
,
Ctr
,
4
),
REG
(
NULL
,
"ctr"
,
NULL
,
Ctr
,
4
),
REG
(
NULL
,
"xer"
,
Xer
,
4
),
REG
(
NULL
,
"xer"
,
NULL
,
Xer
,
4
),
REG
(
"fpu"
,
"f0"
,
Fpr0
,
4
),
REG
(
"fpu"
,
"f0"
,
Fpr0
,
4
),
REG
(
NULL
,
"f1"
,
Fpr1
,
4
),
REG
(
NULL
,
"f1"
,
Fpr1
,
4
),
...
...
programs/winedbg/be_x86_64.c
View file @
771463ad
...
@@ -768,67 +768,67 @@ static BOOL be_x86_64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
...
@@ -768,67 +768,67 @@ static BOOL be_x86_64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
}
#define REG(f,n,
r,gs) {f, n
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
#define REG(f,n,
t,r,gs) {f, n, t
, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static
struct
gdb_register
be_x86_64_gdb_register_map
[]
=
{
static
struct
gdb_register
be_x86_64_gdb_register_map
[]
=
{
REG
(
"core"
,
"rax"
,
Rax
,
8
),
REG
(
"core"
,
"rax"
,
NULL
,
Rax
,
8
),
REG
(
NULL
,
"rbx"
,
Rbx
,
8
),
REG
(
NULL
,
"rbx"
,
NULL
,
Rbx
,
8
),
REG
(
NULL
,
"rcx"
,
Rcx
,
8
),
REG
(
NULL
,
"rcx"
,
NULL
,
Rcx
,
8
),
REG
(
NULL
,
"rdx"
,
Rdx
,
8
),
REG
(
NULL
,
"rdx"
,
NULL
,
Rdx
,
8
),
REG
(
NULL
,
"rsi"
,
Rsi
,
8
),
REG
(
NULL
,
"rsi"
,
NULL
,
Rsi
,
8
),
REG
(
NULL
,
"rdi"
,
Rdi
,
8
),
REG
(
NULL
,
"rdi"
,
NULL
,
Rdi
,
8
),
REG
(
NULL
,
"rbp"
,
Rbp
,
8
),
REG
(
NULL
,
"rbp"
,
"data_ptr"
,
Rbp
,
8
),
REG
(
NULL
,
"rsp"
,
Rsp
,
8
),
REG
(
NULL
,
"rsp"
,
"data_ptr"
,
Rsp
,
8
),
REG
(
NULL
,
"r8"
,
R8
,
8
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
,
8
),
REG
(
NULL
,
"r9"
,
R9
,
8
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
,
8
),
REG
(
NULL
,
"r10"
,
R10
,
8
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
,
8
),
REG
(
NULL
,
"r11"
,
R11
,
8
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
,
8
),
REG
(
NULL
,
"r12"
,
R12
,
8
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
,
8
),
REG
(
NULL
,
"r13"
,
R13
,
8
),
REG
(
NULL
,
"r13"
,
NULL
,
R13
,
8
),
REG
(
NULL
,
"r14"
,
R14
,
8
),
REG
(
NULL
,
"r14"
,
NULL
,
R14
,
8
),
REG
(
NULL
,
"r15"
,
R15
,
8
),
REG
(
NULL
,
"r15"
,
NULL
,
R15
,
8
),
REG
(
NULL
,
"rip"
,
Rip
,
8
),
REG
(
NULL
,
"rip"
,
"code_ptr"
,
Rip
,
8
),
REG
(
NULL
,
"eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"cs"
,
SegCs
,
4
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
,
4
),
REG
(
NULL
,
"ss"
,
SegSs
,
4
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
,
4
),
REG
(
NULL
,
"ds"
,
SegDs
,
4
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
,
4
),
REG
(
NULL
,
"es"
,
SegEs
,
4
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
,
4
),
REG
(
NULL
,
"fs"
,
SegFs
,
4
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
,
4
),
REG
(
NULL
,
"gs"
,
SegGs
,
4
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
,
4
),
{
NULL
,
"st0"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
0
]),
10
,
10
},
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
0
]),
10
,
10
},
{
NULL
,
"st1"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
1
]),
10
,
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
1
]),
10
,
10
},
{
NULL
,
"st2"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
2
]),
10
,
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
2
]),
10
,
10
},
{
NULL
,
"st3"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
3
]),
10
,
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
3
]),
10
,
10
},
{
NULL
,
"st4"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
4
]),
10
,
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
4
]),
10
,
10
},
{
NULL
,
"st5"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
5
]),
10
,
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
5
]),
10
,
10
},
{
NULL
,
"st6"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
6
]),
10
,
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
6
]),
10
,
10
},
{
NULL
,
"st7"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
7
]),
10
,
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
7
]),
10
,
10
},
REG
(
NULL
,
"fctrl"
,
u
.
FltSave
.
ControlWord
,
4
),
REG
(
NULL
,
"fctrl"
,
NULL
,
u
.
FltSave
.
ControlWord
,
4
),
REG
(
NULL
,
"fstat"
,
u
.
FltSave
.
StatusWord
,
4
),
REG
(
NULL
,
"fstat"
,
NULL
,
u
.
FltSave
.
StatusWord
,
4
),
REG
(
NULL
,
"ftag"
,
u
.
FltSave
.
TagWord
,
4
),
REG
(
NULL
,
"ftag"
,
NULL
,
u
.
FltSave
.
TagWord
,
4
),
REG
(
NULL
,
"fiseg"
,
u
.
FltSave
.
ErrorSelector
,
4
),
REG
(
NULL
,
"fiseg"
,
NULL
,
u
.
FltSave
.
ErrorSelector
,
4
),
REG
(
NULL
,
"fioff"
,
u
.
FltSave
.
ErrorOffset
,
4
),
REG
(
NULL
,
"fioff"
,
NULL
,
u
.
FltSave
.
ErrorOffset
,
4
),
REG
(
NULL
,
"foseg"
,
u
.
FltSave
.
DataSelector
,
4
),
REG
(
NULL
,
"foseg"
,
NULL
,
u
.
FltSave
.
DataSelector
,
4
),
REG
(
NULL
,
"fooff"
,
u
.
FltSave
.
DataOffset
,
4
),
REG
(
NULL
,
"fooff"
,
NULL
,
u
.
FltSave
.
DataOffset
,
4
),
REG
(
NULL
,
"fop"
,
u
.
FltSave
.
ErrorOpcode
,
4
),
REG
(
NULL
,
"fop"
,
NULL
,
u
.
FltSave
.
ErrorOpcode
,
4
),
REG
(
"sse"
,
"xmm0"
,
u
.
s
.
Xmm0
,
16
),
REG
(
"sse"
,
"xmm0"
,
"vec128"
,
u
.
s
.
Xmm0
,
16
),
REG
(
NULL
,
"xmm1"
,
u
.
s
.
Xmm1
,
16
),
REG
(
NULL
,
"xmm1"
,
"vec128"
,
u
.
s
.
Xmm1
,
16
),
REG
(
NULL
,
"xmm2"
,
u
.
s
.
Xmm2
,
16
),
REG
(
NULL
,
"xmm2"
,
"vec128"
,
u
.
s
.
Xmm2
,
16
),
REG
(
NULL
,
"xmm3"
,
u
.
s
.
Xmm3
,
16
),
REG
(
NULL
,
"xmm3"
,
"vec128"
,
u
.
s
.
Xmm3
,
16
),
REG
(
NULL
,
"xmm4"
,
u
.
s
.
Xmm4
,
16
),
REG
(
NULL
,
"xmm4"
,
"vec128"
,
u
.
s
.
Xmm4
,
16
),
REG
(
NULL
,
"xmm5"
,
u
.
s
.
Xmm5
,
16
),
REG
(
NULL
,
"xmm5"
,
"vec128"
,
u
.
s
.
Xmm5
,
16
),
REG
(
NULL
,
"xmm6"
,
u
.
s
.
Xmm6
,
16
),
REG
(
NULL
,
"xmm6"
,
"vec128"
,
u
.
s
.
Xmm6
,
16
),
REG
(
NULL
,
"xmm7"
,
u
.
s
.
Xmm7
,
16
),
REG
(
NULL
,
"xmm7"
,
"vec128"
,
u
.
s
.
Xmm7
,
16
),
REG
(
NULL
,
"xmm8"
,
u
.
s
.
Xmm8
,
16
),
REG
(
NULL
,
"xmm8"
,
"vec128"
,
u
.
s
.
Xmm8
,
16
),
REG
(
NULL
,
"xmm9"
,
u
.
s
.
Xmm9
,
16
),
REG
(
NULL
,
"xmm9"
,
"vec128"
,
u
.
s
.
Xmm9
,
16
),
REG
(
NULL
,
"xmm10"
,
u
.
s
.
Xmm10
,
16
),
REG
(
NULL
,
"xmm10"
,
"vec128"
,
u
.
s
.
Xmm10
,
16
),
REG
(
NULL
,
"xmm11"
,
u
.
s
.
Xmm11
,
16
),
REG
(
NULL
,
"xmm11"
,
"vec128"
,
u
.
s
.
Xmm11
,
16
),
REG
(
NULL
,
"xmm12"
,
u
.
s
.
Xmm12
,
16
),
REG
(
NULL
,
"xmm12"
,
"vec128"
,
u
.
s
.
Xmm12
,
16
),
REG
(
NULL
,
"xmm13"
,
u
.
s
.
Xmm13
,
16
),
REG
(
NULL
,
"xmm13"
,
"vec128"
,
u
.
s
.
Xmm13
,
16
),
REG
(
NULL
,
"xmm14"
,
u
.
s
.
Xmm14
,
16
),
REG
(
NULL
,
"xmm14"
,
"vec128"
,
u
.
s
.
Xmm14
,
16
),
REG
(
NULL
,
"xmm15"
,
u
.
s
.
Xmm15
,
16
),
REG
(
NULL
,
"xmm15"
,
"vec128"
,
u
.
s
.
Xmm15
,
16
),
REG
(
NULL
,
"mxcsr"
,
u
.
FltSave
.
MxCsr
,
4
),
REG
(
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
u
.
FltSave
.
MxCsr
,
4
),
};
};
struct
backend_cpu
be_x86_64
=
struct
backend_cpu
be_x86_64
=
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment